PCI-SIG Developers Conference 2017 – PCI-SIG, the organization responsible for the widely adopted PCI Express (PCIe) industry-standard input/output (I/O) technology, today announced 32GT/s as the next progression in speed for the PCIe 5.0 architecture, targeting high-performance applications such as artificial intelligence, machine learning, gaming, visual computing, storage and networking. Slated for completion in 2019, the specification development is well underway with Revision 0.3 already available to PCI-SIG member companies.
“In our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O,” said Al Yanes, PCI-SIG Chairman and President. “PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs.”
The preceding PCIe 4.0 specification is designed with key functional enhancements that future-proof the PCIe architecture design, thereby accelerating future specification development. This undertaking, along with improved silicon design processes, serves as the foundation for the PCIe 5.0 specification.
For high-end networking like 400Gb Ethernet solutions and dual 200Gb/s InfiniBand, the PCIe 5.0 architecture operates at full duplex and provides up to 128GB/s in bandwidth. The higher bandwidth will serve accelerator and GPU attachments, as well as constricted form factor applications needing to increase channel width.
“With the onset of Big Data, high-performance applications and the arrival of next generation non-volatile memories, storage devices have a voracious appetite for increasing performance,” said Amber Huffman, President of NVM Express, Inc. “We are pleased to see the PCI-SIG continue to evolve this interface technology to enable NVMe SSDs for the enterprise and data center to leverage the scalability of the PCIe architecture, both in higher bandwidth and lower latency.”