AMD next-generation EPYC socket SP3r2 processor codename “Rome,” which is a multi-chip module of 9 chiplets (up from four). While first-generation EPYC MCMs (and Ryzen Threadripper) were essentially “4P-on-a-stick,” the new “Rome” MCM takes the concept further, by introducing a new centralized uncore component called the I/O die. Up to eight 7nm “Zen 2” CPU dies surround this large 14 nm die, and connect to it via the substrate, using InfinityFabric, without needing a silicon interposer. Each CPU chiplet features 8 cores, and hence we have 64 cores in total.
As you can see the actual CPU dies themselves are significantly smaller than current-generation “Zeppelin” dies. While the transition to 7 nm can be expected to significantly reduce die size, groups of two dies appear to be making up the die-area of a single “Zeppelin.” It’s possible that the CPU chiplets in “Rome” physically lack an integrated northbridge and southbridge, and only feature a broad InfinityFabric interface. The I/O die handles memory, PCIe, and southbridge functions, featuring an 8-channel DDR4 memory interface that’s as monolithic as Intel’s implementations, a PCI-Express gen 4.0 root-complex, and other I/O.